What a layout-design is
A layout-design is the layout of transistors and other circuit elements, and the lead wires that connect them, as expressed in a semiconductor integrated circuit, or chip. India protects it through a law of its own, because the Patents Act excludes topographies of integrated circuits.
The Semiconductor Integrated Circuits Layout-Design Act, 2000 (Act No. 37 of 2000, assented to on 4 September 2000) defines a layout-design as "a layout of transistors and other circuitry elements and includes lead wires connecting such elements" (s.2(h)). Section 3(o) of the Patents Act lists topographies of integrated circuits among the things that are not inventions.[1] [3]
Original
It must be the result of its creator’s own intellectual efforts and not commonly known to designers and manufacturers when created. A combination of commonly known elements can qualify if the whole meets that test (s.7).[1]
Not yet exploited
It cannot have been commercially exploited in India or a convention country. Exploitation within two years before the filing date is disregarded (s.7).[1]
Distinctive
It must be inherently distinctive and inherently capable of being distinguished from other registered layout-designs (s.7).[1]
The legal framework
The Act is administered by the Registrar of the Semiconductor Integrated Circuits Layout-Design Registry, which one explainer places under the Ministry of Electronics and Information Technology, in New Delhi.[4] The Semiconductor Integrated Circuits Layout-Design Rules, 2001 (G.S.R. 892(E), 10 December 2001) set out the procedure.[2]
| Provision | What it says |
|---|---|
| s.7 | Conditions for registration, as above. For a design made under a commission or employment contract, the right to register belongs to the commissioner or employer unless the contract says otherwise. |
| s.15 | Registration lasts ten years, counted from the earlier of the filing date or the first commercial exploitation in India or anywhere. |
| s.17 | A valid registration gives the proprietor the exclusive right to use the layout-design and to seek relief for infringement, whether or not it is incorporated in an article. |
| s.18 | Infringement includes reproducing a registered design in whole or part, and importing, selling or distributing a protected design, a circuit containing it, or an article containing such a circuit, for commercial purposes. Exceptions include reproduction for evaluation, analysis, research or teaching, creating an original design after evaluating a registered one, innocent infringers who may continue on existing stock for a royalty, goods put on the market with the proprietor’s consent, and independently created identical designs. |
| s.19 | The registration and later assignments are prima facie evidence of validity. |
| ss.24-29 | Registered users: someone other than the proprietor may be registered as a registered user under a written agreement. |
How a layout-design is registered
The Rules set these stages. I read the Rules in part, so treat the outline as a guide and check the full text.[2]
- ApplyForm LD-1 with the prescribed fee. Drawings or photographs must be at least 20 times the size of the fabricated circuit. Secrecy of parts can be requested.Rules 22(1)-(3)
- AdvertiseAn accepted application is advertised in the journal.Rule 30
- OpposeOpposition on Form LD-2 within three months of advertisement.Rule 33
- RegisterRegistration follows after three months from advertisement, subject to s.13(1). If an applicant does not reply to objections within three months the application is deemed abandoned.Rules 44, 25
Penalties
Infringement (s.56)
Knowing and wilful contravention of s.18 carries up to three years’ imprisonment, a fine of INR 50,000 to INR 10 lakh, or both.[1]
False claims (ss.57-58)
Falsely claiming a layout-design is registered, or falsely claiming a connection with the Registry, carries up to six months’ imprisonment, a fine, or both.[1]
Falsifying the register (s.59)
Up to two years’ imprisonment, a fine, or both. Courts may order forfeiture of goods used in s.56 offences (s.60).[1]
What this page does not cover
- Registration numbers. The annual report I used for the other pages does not cover this registry, and I did not find figures for it.
- The Rules after rule 91 and the part of the Act text beyond section 96, which I could not read in full.
- Amendments after 2001, including changes to the appellate body that the Rules name as the Appellate Board.
- Case law. I did not search for decisions under the Act.
References
Links are pages I opened while building this page. Where a source is a law-firm or explainer article rather than the Act itself, it is labelled secondary.
- The Semiconductor Integrated Circuits Layout-Design Act, 2000 (Act No. 37 of 2000). WIPO Lex, text. Sections 2, 7, 15, 17, 18, 19, 24-29 and 56-60 read. The text was truncated at s.96.
- Semiconductor Integrated Circuits Layout-Design Rules, 2001. WIPO Lex, text. Read in part.
- Patents Act, 1970, section 3(o). ipindia.gov.in.
- Semiconductor Integrated Circuit Layout Design Act, 2000. iPleaders. secondary Used for the Registry’s location and ministry.